Zip CPU

@zipcpu

FPGA design engineer and blogger, placing particular emphasis on test and formal verification

Gisselquist Technology, LLC,
Vrijeme pridruživanja: siječanj 2017.

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  1. Prikvačeni tweet
    4. lis 2018.

    Wow, lots of new twitter followers just joined. Welcome! Just to give you an opportunity to get to know me and the ZipCPU blog, here's a bit about me and what you can expect here: Again, welcome!

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  2. prije 15 sati

    For those who've enjoyed my Formal Verification quizzes on twitter, I've now posted the first 11 together with their answers on the blog. You can read the most recent question, and now the answer, for quiz #11 posted today here.

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  3. prije 17 sati

    The new PLL, together with its test bench, has now been added to my collection of digital PLL cores. Feel free to check them out here:

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  4. prije 17 sati

    This shouldn't be a really surprising result, any algorithm should be able to do "better" with better information. Indeed, if you compare this PLL with the one I posted two years ago, you'll find all but the phase error detector is the same

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  5. prije 17 sati

    The Digital PLL used by the SDR project is different from the one I blogged about some time back: it takes I+Q inputs, vs just a digital sinewave (more rectangle wave) input. As such, it tracks and locks twice as fast.

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  6. proslijedio/la je Tweet
    5. velj

    Hi. We are Digilent and we are going to be at in Nuremberg this month (Booth 3-610). We'll have a bunch of demos and things you can touch. Who's with us?!

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  7. 5. velj

    Here's the reddit link, and the Xilinx forum link, The IRC channel the above logs are from isn't currently being automatically recorded.

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  8. 5. velj

    Some screen shots from a discussion of building an AXI master. Since the question has now been posted on both Xilinx's forums and Reddit, I figured I'd offer some background here:

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  9. proslijedio/la je Tweet
    5. velj
    Odgovor korisnicima

    Not everything that reads instructions from memory and acts upon them needs to be a CPU.

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  10. 5. velj

    The image above shows the various output pins, each firing for a known (user adjustable) on-time, and each offset from the next by a known time-delay (frequency). In the middle of the trace, the delay changes. Now I've just got a lot of software bugs to fix.

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  11. 5. velj

    Most commodity FPGAs don't have enough block RAM to delay this many elements this deep. I had to find another approach. This is the first simulation trace I've examined, and it shows my delay unit working--the first time. (Thank you, formal!)

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  12. 5. velj

    The specs on the beamformer were more difficult than I was expecting. It needs to be able to delay each element by hundreds of microseconds. I wanted to be able to also delay each by units of single (10ns) clocks as well. Getting this to fit in an FPGA was a challenge

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  13. 5. velj

    Here's a cool effect within a gtkwave trace image. I wasn't expecting it to have a pattern like this, but ... it all makes sense. See ... I'm building a SONAR beamformer ...

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  14. 4. velj

    For those interested, I just pushed my SDR work using 's SX1257 Pmod to github. Feel free to check it out!

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  15. 2. velj

    Building a radio using a pair of SX1257s from and two icebreakers from . Hardware compliments of . AM and FM are fairly easy, and fit nicely. Whether I can get the 16QAM link to fit still remains to be determined

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  16. proslijedio/la je Tweet
    1. velj
    Odgovor korisniku/ci
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  17. 31. sij

    The "better interpolator" article chases the concept of the "mother spline" function: A function which can be used to analyze exact or approximate spline functions which don't require a linear equation solution, and thus can be applied to infinite sequences.

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  18. 31. sij

    Rereading my old article on Quadratic interpolation reminds me that I promised to write an article on how to do better. That better interpolator article is only partially written, but the one above is still well worth reading and knowing.

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  19. 31. sij

    The design was intended to be run-time configurable, where you would set the number of averages at runtime. The difficult part is bit growth. Every round has a gain of N. K rounds has a gain of N^K. How many bits do you need to represent that? Ouch.

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  20. 31. sij

    After four rounds of averaging N samples, then decimating by N/2 guarantees that the out of band junk is at least 70dB down, while minimizing the in-band distortion. What do you think?

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  21. 31. sij

    Reviewing my CIC implementation yesterday, I'd note that it's kind of unique. Instead of averaging by N and decimating by N, it averages by N and then decimates by N/2. Further, it allows the filter (not the decimation) to be repeated an arbitrary number of times. 4 seems good

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