Imagine a worst case scenario: the TLB caches nothing.
That would mean that in order to read anything from L2/L3 CPU caches you'd always need to lookup the correct address in RAM first. That would be terrible for performance!
So giving your TLB cache a better time is good! 
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The reason why Big Pages make a difference is allows more memory to be can addressed using fewer addresses. Each entry in the cache can suddenly represent multiple megabytes; not just 4kb chunks. Whether that's useful definitely depends on what kind of application you write tho.
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do you mind sharing the title of the book please.
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Systems performance: Enterprise and the cloud.
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