Thanks!!
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Have you read Kaeslin's book? https://www.amazon.com/dp/0521882672
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Thanks!
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It would be fantastic if you would join the open source chip design community.
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a trend since 2007 is to allow for short general/codable feedback loops, see [cuda core]. a trend since 2011 is to make slower but more parallel hardware.for 3 spatial domains, more efficient than rushing 1 time domain,since 2014, its about fast networks with FFT specialization.
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the problem of modern transistor-networks is that it is computer aided design, often with evolutionary-methods or neural-net-designed, to a point where people admit to have lost an overview, due to rapidly changing complexity.
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