to clarify, I'm only interested in a single initiator I2C systems (i.e. specifically *not* multi-master topologies)
-
-
Prikaži ovu nitHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi
-
-
-
I've worked with several dozen slave devices (mostly sensors), a couple of master cells, and even RTL for master/slave implementations, and I've never seen this. I suspect a lot of masters can't even do it, and I haven't seen a software API that could express it if they could.
-
that's exactly why I'm asking: I have a master that can't do it (FX2), at least not in a documented way (I -did- manage to exploit a race condition in their I2C peripheral to do it, but, ew), and I'm designing a software API right now
- Još 2 druga odgovora
Novi razgovor -
-
-
errr, not anything that's to spec?
-
I'm even literally writing an i2c bus master driver and a bunch of peripherals for an OS and nothing I've ever seen does this. Honestly, if you find a device that does then it wouldn't be so bad to add a custom call to do the crazy thing..
Kraj razgovora
Novi razgovor -
-
-
Yes, when exploiting a poorly designed i2c state machine
Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi
-
-
-
Maybe some sort of read + modify + write?! Could be necessary in multi master topologies?
Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi
-
-
-
There is a common power controller bus which is basically I2C but has mandatory restarts like you describe. (Can’t recall the name)
-
If you're thinking of PMBus, it (and SMBus generally) uses write-then-read, not read-then-write
Kraj razgovora
Novi razgovor -
Čini se da učitavanje traje već neko vrijeme.
Twitter je možda preopterećen ili ima kratkotrajnih poteškoća u radu. Pokušajte ponovno ili potražite dodatne informacije u odjeljku Status Twittera.