Discuss on HN: https://news.ycombinator.com/item?id=22077974 …
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But why does using AVX-512 on Xeons literally wear out and destroy the CPUs? What's the mechanism?
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It's mentioned in the article, but basically the CPU has to run in a mode where the worst-case voltage drop is less than the minimum voltage to run stably at a different frequency. Voltage drop occurs due to a rapid change in demanded current from the core: positive dI/dt ...
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Remember that many AVX instructions can be encoded with two possible prefixes - VEX or EVEX, and that EVEX can still encode 32/64/128/256 bit insts. It might be interesting to investigate whether it's the *bit width* or the *prefix used* that triggers some of these behaviours?
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I mention it in a couple places but it's always the width: EVEX encoded stuff behaves the same as VEX encoded stuff of the same width. So you can use AVX-512 stuff without suffering any frequency reduction as long as you don't use 512-bit width *. * or heavy 256-bit ops.
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First bullet in the summary seems to be missing the actual period of time ("After a period of about [???] not using ...")
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Thanks, the summary is probably the lowest quality part because I was the most tired when I wrote it. Fixed and credited (it's roughly 680 μs).
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Is a "performance transitions party" anything like an "endian reveal party"? Try not to set anything on fire.
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What did you use for the charts? Python + Matplotlib?
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I include some detail on reproducibility here: https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html#the-source … Plots are specified a shell script (http://plots.sh ), which calls this Python script: https://github.com/travisdowns/freq-bench/blob/post1/scripts/plot-csv.py … ... which uses matplotlib.
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Čini se da učitavanje traje već neko vrijeme.
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