Wrote a mini CSP in static C for bare metal uC work. Needs some real-world use testing still, but I like how it turns out to be fairly simple. github.com/zwizwa/uc_tool
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I had been looking for a "mini Erlang" before, but really CSP's synchronous nature is a much better fit for static allocation. I learned a couple of surprising things doing this. See comments in csp_test.c csp.c csp.h
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Also started porting the ideas to Seq (Haskell->Verilog macro lang) to be able to use on FPGA. I'd like to be able to write in a style that makes it possible to migrate tasks along the stack: FPGA-uC-Linux. Starting to believe this is within reach.
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I have a first draft of CSP style channels in Seq. Probably reinventing things, but deriving this was an interesting process. The trick is that while rendez-vous is symmetric in principle, inserting the delay-breaking register makes the code asymmetric.
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See comments for closeChannel, about halfway through in github.com/zwizwa/asm_too
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So basically reader and writer have a circular dependency, and if data flows only in one direction, it is best broken where the circle is "thin", i.e. where there is only a single ready signal. Similar to a bus transaction (req/ack) but not quite: writer can sit there waiting.
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So the implementation is asymmetric. The meaning is still symmetric: it still implements rendez-vous. Reader or writer can arrive early and wait until the other party arrives, which then creates a transaction, and both continue after that, or immediately rendez-vous again.