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If only there was something better out there... 🤔

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Apr 16, 2019

Learning the do's and don't's of System Verilog. Turns out it's mostly don't's. I have no idea if people are using it wrong or if it's just not possible to use right. This is the most incoherent thing I have ever seen

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Yeah I know. Strange isn't it. I guess I need to invent my own language and convince people to use it. Just need a starting point. Hmm... JVM is pretty nifty but I want a functional language instead of Java. I know! I'll base it on Clojure and the language will be called Gouge!

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Switching for hardware description to hardware construction has always seemed like a big leap to me. How come people take that route instead of metaprogramming on top of Verilog?

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Exactly. Here's an attempt: github.com/zwizwa/asm_too I like it, but I wish I had gone the extra mile and encode signal types as Haskell types. I didn't know how when I started. Maybe for version 2 after I finish the (closed source) application that uses it.

12:11 PM · Apr 17, 2019Twitter Web Client