I am nerd sniped: how many incorrectly speculated instructions can you get to run in a single shot and how are those conditions engineered? /cc:@tehjh
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(context: reorder buffer size is documented in the optimization manual for Intel stuff, goes up to 192 or something in that ballpark)
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I've mostly been assuming that the reorder buffer size is a hard limit, but maaaaybe the CPUs work around that?
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Certainly the rob size is the most important factor
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reorder buffer size matters . Intel had increased rob from 160 to 226 between sandy and sky. Some uOps can be compled without execution and can be resolved by renaming register. Those never enter the rob
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simple stuff like "mov rax, rbx" and "xor rax, rax", right?
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