Good explanation of the compute architecture of GPGPUs: SIMD < SIMT < SMT: parallelism in NVIDIA GPUs #gpgpu http://yosefk.com/blog/simd-simt-smt-parallelism-in-nvidia-gpus.html …
-
-
so iow a switch with many branches is inefficient because most time is spent not doing anything?
-
yeah, basically. at best, the dead lanes can be clock gated (but even that's not always possible)
- 1 more reply
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.