random thought: if PTEs had per-CPU "accessed" bits, you could have more precise TLB flush IPIs and maybe make rapid memory mapping modifications in highly concurrent contexts faster?
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Replying to @tehjh
Where would you fit the bits on a high core count platform?
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Replying to @smattrr
good question. :P maybe for stuff that's mostly local to a single core, you could not have one bit per CPU, but instead use a few bits to store the ID of the first core that accessed it, and then the second core sets it to a reserved value?
9:05 AM - 26 Oct 2018
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