random thought: if PTEs had per-CPU "accessed" bits, you could have more precise TLB flush IPIs and maybe make rapid memory mapping modifications in highly concurrent contexts faster?
-
-
Replying to @tehjh
what sort of workloads would this benefit.. in other words what workloads have high tlb shootdowns
1 reply 0 retweets 0 likes
Replying to @p_r
I didn't say it was a particularly good thought. :P
It might be interesting if your memory allocator (ab)uses page tables for use-after-free detection/mitigation, like @DanielMicay's https://github.com/AndroidHardening/hardened_malloc … .
0 replies
0 retweets
2 likes
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.