random thought: if PTEs had per-CPU "accessed" bits, you could have more precise TLB flush IPIs and maybe make rapid memory mapping modifications in highly concurrent contexts faster?
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Replying to @tehjh
pres can get filled speculative.. not so sure there is a guarantee that the A bit always gets set for that
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Replying to @fenruspdx
Intel SDM 3A 4.10.2.3: "the processor does not cache a translation for a page number unless the accessed flag is 1 in each of the paging-structure entries used during translation; before caching a translation, the processor sets any of these accessed flags that is not already 1."
7:41 AM - 26 Oct 2018
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