Where would you fit the bits on a high core count platform?
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good question. :P maybe for stuff that's mostly local to a single core, you could not have one bit per CPU, but instead use a few bits to store the ID of the first core that accessed it, and then the second core sets it to a reserved value?
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what sort of workloads would this benefit.. in other words what workloads have high tlb shootdowns
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I didn't say it was a particularly good thought. :P It might be interesting if your memory allocator (ab)uses page tables for use-after-free detection/mitigation, like
@DanielMicay's https://github.com/AndroidHardening/hardened_malloc … .
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pres can get filled speculative.. not so sure there is a guarantee that the A bit always gets set for that
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Intel SDM 3A 4.10.2.3: "the processor does not cache a translation for a page number unless the accessed flag is 1 in each of the paging-structure entries used during translation; before caching a translation, the processor sets any of these accessed flags that is not already 1."
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CR3 is percpu. So page tables can be as well.
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