Symbiotic EDA

@symbiotic_eda

smart EDA empowerment, Yosys SymbiYosys Formal Methods Risc-V FPGA Verilog

Wien, Österreich
Vrijeme pridruživanja: rujan 2017.

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  1. proslijedio/la je Tweet

    Around 2012 my colleagues and I worked on Intel ME We were bug hunters We read the code Line by line For months 1 team of many Want to tell me formal methods are too expensive? I've done code reviews I've done FM It's time to talk about it

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  2. proslijedio/la je Tweet

    Flying home from ! Extra big Thank You to everyone who took the time to chat! To the undergrads, grads, post docs, profs, and industry colleagues: This is your year! Let’s do it! Formal methods NOW!

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  3. proslijedio/la je Tweet

    I have never left an InfoSec conf feeling anything but depressed Leaving , I am thankful to be alive in this exciting time Hard truth for my InfoSec peers: our work is depressing because INFOSEC DOES NOT WORK Show me a secure system w/o Formal Methods You can’t

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  4. proslijedio/la je Tweet
    23. sij

    Yahoo! Final part of the "introduction to Formal Verification" series is now available on youtube:

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  5. 21. sij

    What's the difference between the Open Source and paid versions of our Formal Verification tools? Join 's webinar tomorrow evening to find out:

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  6. proslijedio/la je Tweet
    16. sij

    Student: [This trainer] had been in the trenches through immersion, and was willing to show what [he] did in the past, now, and why [he] made the changes in what he was doing. Student: Fantastic!

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  7. proslijedio/la je Tweet
    16. sij

    the material any time to become stale. Q: Compared to other HDL courses? Student: Clearly at the top. Also took a course from a major vendor's FAE. Was all very basic--not worth the time. Q: The qualification of the trainer for giving the course was _____ Student: Great!

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  8. proslijedio/la je Tweet
    16. sij

    I finished teaching one of my formal verification courses today. Given the course critique question: I liked the way the material was taught ______ Student reply: Yes! Very much so! The slides, discussion, followed by the immediate lab were really great! They didn't allow ..

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  9. proslijedio/la je Tweet
    16. sij

    I don't trust anybody who says Model Checking/Static Functional Verification is easy, if he/she haven't read at least one of these books before. Either he/she doesn't fully understand it really, or just wants to sell something.

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  10. 13. sij

    Our next webinar with looks at how to install the Formal Verification tools. We also compare the Open Source version to the paid version. Wednesday, January 22nd 2020 - 6:00 PM (CET). Register here:

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  11. proslijedio/la je Tweet
    11. sij

    Hamid Shojaei on the benefits of continuous integration for RTL development

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  12. proslijedio/la je Tweet
    1. sij

    Happy New Year! Today, I'm going to declare 2019 to be the "Year when AXI met formal verification"! Today's article showcases ZipCPU blog highlights from 2019, most popular articles, AXI bugs found, and more

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  13. proslijedio/la je Tweet
    27. pro 2019.

    Implemented BNE and BEQ instructions and simplified the design a bit. And the nice thing is, is that because I formally verify the design, I can fearlessly refactor the implementation, knowing that the design will still work correctly.

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  14. proslijedio/la je Tweet
    23. pro 2019.

    It only took a couple minutes with SymbiYosys to turn up the following trace. This then sends you looking back at the code to see what caused the problem

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  15. proslijedio/la je Tweet
    23. pro 2019.

    In the last video I made for I introduced K-Induction, which can prove your design is good for all time. In this penultimate episode of the series, we dig a bit deeper into the challenges of K-Induction

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  16. proslijedio/la je Tweet
    17. pro 2019.

    The biggest FPGA use case for an AXI->WB bridge are the SoC chips such as Xilinx's Zynqs. An AXI->WB bridge together with a WB interconnect will vastly simplify peripheral design and verification.

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  17. proslijedio/la je Tweet
    19. pro 2019.

    This pattern has become so routine, I hardly think about it any more.

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  18. proslijedio/la je Tweet
    14. pro 2019.

    I don't get it. Why have a bus that allows separate read and write channels, when either the interconnect or the slave only ever allows a single read or write transfer at a time and never both? It just doubles the logic for no performance gain.

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  19. 20. pro 2019.

    New blog post - finding bugs with formal verification tools. Thanks for the writeup of your experience!

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  20. proslijedio/la je Tweet
    16. pro 2019.

    Use any buses inside your designs? Even if you've never heard of Formal Verification, has prepared some great slides that will help you to avoid bus lockup. Webinar is this Wednesday! Register here:

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