sakamoto.kazuki

@splhack

Software Engineer who loves FPGA

San Francisco Bay Area
Vrijeme pridruživanja: travanj 2007.

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  1. Prikvačeni tweet
    12. kol 2018.

    BX → Verilog Sprite Controller → VGA → LCD 🎉

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  2. 3. velj

    this emulator is pretty neat for generating test cases for my design😊

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  3. 3. velj
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  4. 30. sij

    LD r,r' / LD r,n / LD r,(HL)

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  5. 30. sij

    This journey 1% finished (actually 3.125%)

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  6. 28. sij
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  7. 28. sij

    writing Z80 with test-driven development🤖

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  8. 25. sij

    5A-75B (Lattice ECP5-25 FPGA 25k LUT) + FT2232HL (for OpenOCD JTAG) + shipping = ~$30, not bad😘

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  9. proslijedio/la je Tweet
    18. sij
    Odgovor korisniku/ci
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  10. proslijedio/la je Tweet
    22. sij
    Odgovor korisnicima

    Check out this repo: . Information on the ColorLight 5A-75B is being updated daily.

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  11. proslijedio/la je Tweet
    24. sij

    New Part Day: LED Driver is FPGA Dev Board in Disguise Our new part of the day is the ColorLight 5A-75B, a board that’s meant to drive eight of those ubiquitous high-density color LED panels over gigabit Ethernet. If you were building a commercial LED w…

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  12. 24. sij

    instruction fetch='read memory to instruction latch' vs memory read='read memory to a 8bit register'?

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  13. 24. sij

    Z80 instruction fetch is 2 clocks long (M1 cycle, T1/T2 fetch, T3/T4 refresh), but memory read is 3 clocks long. what is the difference?🤔

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  14. 22. sij

    how `ld r,r'` works?🤔 write r first, and read r'??

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  15. 22. sij

    why it writes data to address latch from IR register on M1 T3, and writes back to IR register on T4?? no one is using it🤔 ... ... oh, this is the memory refresh!

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  16. 19. sij

    🤔.oO(Tri-state, inout, more than one output connected to an input -> Mux)

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  17. 16. sij

    Writing Z80 from circuit would be exactly feeling like playing MHRD!

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  18. 16. sij

    printed out A-Z80 circuits to write Z80😁

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  19. 16. sij

    named tuple (magma HDL Product type) is pretty neat, isn't it.

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  20. 13. sij

    Sprite Attribute is back! Sprite + Scanline + VGA on TinyFPGA BX. Written in Python with magma → Verilog.

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  21. 9. sij

    Everything now works as expected after modernizing Python code with magma hwtypes2 🥳

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