After some changes, at a clock speed of 200Mhz, each non SB/LB instruction retires in ~12.48ns This means I should be seeing a throughput of ~80MIPS during peak 'register-only' work. Time to add some counter support so I can see actual figures and perhaps also run Dhrystone.
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(During very memory intensive work, this drops to about 44MIPS)
10:58 PM - 4 Jan 2021
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