Engin Cilasun  

@sparsevoxel

Principal Core Engineer Graphics/Systems/GPGPU/SoC(riscv) Doesn’t eat animals. All ideas my own.

New York City - New York
Joined March 2011
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  1. Jan 24

    I wonder if the power analysis of Vivado is good enough for a rough estimate? Sounds too good to be true if the actual power draw when 'dynamic' (i.e. running code) is actually 0.221W for this mini RISCV

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  2. Jan 24

    And all fixed. Somehow broke VRAM memory addressing a bit. I'm now getting funky 80's "metal object touched the expansion slot of my ZX Spectrum" artifacts :)

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  3. Jan 24

    This is curious... My changes to the RISCV core (switched the state machine to one-hot encoding) work perfectly fine in the behavioral simulation, but generate a completely garbage output for synthesis / implementation. Added probes to hardware and indeed it's all gone R2-D2...

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  4. Jan 22

    After some debug sessions, I found out that I forgot to 'zero' the 'zero' register on my new code (because I wrote it in a hurry) No wonder some code has been acting funny :/ Hope this is the only bug. Resuming 3AM hardware debugging :)

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  5. Jan 22

    Weekend RISC-V project is back! I'll be looking at revising the CPU core this weekend, and hopefully get external DDR3 memory working so I don't need to waste on-chip block RAM for code storage and execution. Also need the data cache, all I have for now is an instruction cache :)

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  6. Jan 15

    First time in a long while, I’m just going to sit and play video games all weekend :-)

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  7. Jan 11

    Today is my first day at Activision as Principal Core Engineer. This is very, very exciting to me, don't be fooled by my calm demeanor :)

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  8. Jan 6

    Huh, what do you know, it actually worked on first try :D

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  9. Jan 6

    Rebuilt most of my riscv from scratch in under 2 hours. This time around I've added an instruction cache. In the following image, the no-activity region for the ICACHE shows that the cache doing its job for a short loop filling the VRAM & all bandwidth goes to memory writes.

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  10. Jan 4

    (During very memory intensive work, this drops to about 44MIPS)

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  11. Jan 4

    After some changes, at a clock speed of 200Mhz, each non SB/LB instruction retires in ~12.48ns This means I should be seeing a throughput of ~80MIPS during peak 'register-only' work. Time to add some counter support so I can see actual figures and perhaps also run Dhrystone.

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  12. Jan 4

    What's odd is that I've previously tried bumping the core frequency to 200Mhz and it failed, but today it's working happily at 200Mhz. Must be due to the reduced logic count and better spread of logic between states :)

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  13. Jan 4

    So now... how does one fit DOOM into 64kbytes :-)

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  14. Jan 4

    The riscv core is now stable, however not written exactly the same way as most pro HDL folks would have done it. Aiming to reduce clocks per instruction and tidy up the code in the future. For now, a small boot loader listens on UART and will run any uploaded elf binary.

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  15. Jan 2

    Working on my risc-v CPU implementation today. Managed to reduce the LUT count from 3300 down to 2565 which is a big space savings, and also increased available code memory to 80Kbytes. Found a hang when I do a 'remu' (remainder/unsigned) op though, so that will need some fixing.

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  16. 31 Dec 2020

    After 9 years total (2 in Sweden 🇸🇪 and 7 in USA 🇺🇸) my time with Avalanche comes to an end today. It was a great pleasure to be a part of Mad Max, Just Cause 3, Just Cause 4, Rage 2 and others during my time there. I will post here about what’s next when the time is right :)

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  17. 31 Dec 2020

    Left my riscv system on all night repeatedly sending this message through uart to do some sort of clock-drift / burn-in test and it still keeps going :)

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  18. 30 Dec 2020

    I think this workflow is about a million times faster than rebuilding the SoC every time I change some code :) I wrote a mini terminal program that I can load via uart and send text/images to, for a test of the system. Quite fine especially with code running from RAM now :)

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  19. 30 Dec 2020

    First try, ELF upload+run works on the riscv SoC. Now all I need to do is to hit reset button if I want to upload a new binary, and use my command line tool to send the new ELF over USB UART. Perhaps time to add software access to the i/o ports so I can read sd-cards next...

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  20. 30 Dec 2020

    Shrunk the ROM down to <255 bytes. It now contains the boot loader, waiting for writes to the UART port and copies the incoming binary to RAM. Moving code execution from ROM+RAMoverlay to use only RAM. I should be able to upload and run code without rebuilding the hardware soon:)

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