In many-core CPUs does it make sense to run half the cores on inverted clock (or otherwise phase-shifted, for a split into more than two sets) or have that half's flip-flops triggered on negedge to reduce supply voltage ripple? In particular, in FPGA designs? @adolofsson @jangray
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Давно и проще - самые прожорливые блоки работают по обоим фронтам, а самые производительные части даже асинхронно (умножение например).
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Replying to @LeoYuriev
Any specific examples? I am aware Pentium 4 integer ALUs operated on both edges, but this was since abandoned and it's not a many-core CPU. I am unaware of CPUs with async MUL, are you? AFAIK, most FPGAs don't support flip-flops working on both edges at once (have to choose one).
6:51 AM - 19 Aug 2018
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