In many-core CPUs does it make sense to run half the cores on inverted clock (or otherwise phase-shifted, for a split into more than two sets) or have that half's flip-flops triggered on negedge to reduce supply voltage ripple? In particular, in FPGA designs? @adolofsson @jangray
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High frequency supply decoupling should be handled on chip or in package. Generally too much inductance going through pins to the board, but it will be chip and app dependent.
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