In many-core CPUs does it make sense to run half the cores on inverted clock (or otherwise phase-shifted, for a split into more than two sets) or have that half's flip-flops triggered on negedge to reduce supply voltage ripple? In particular, in FPGA designs? @adolofsson @jangray
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We might give this a try in an attempt to get our sha512crypt design to run at the design tools' expected frequency (where it also draws more power, so we suspect supply voltage ripple is the problem): http://www.openwall.com/lists/john-users/2018/07/23/1 … https://github.com/magnumripper/JohnTheRipper/tree/bleeding-jumbo/src/ztex/fpga-sha512crypt …
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