That would depend on the decoupling capacitors and frequency response of your power delivery network, but in general I would say no.
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Thanks. Considering DC resistance, it'd reduce the peak voltage drop on PCB traces between the decoupling capacitors and the chip as well as on power distribution on die. I thought this could help. I understand impedance at the original vs. multiplied frequency might matter more.
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We might give this a try in an attempt to get our sha512crypt design to run at the design tools' expected frequency (where it also draws more power, so we suspect supply voltage ripple is the problem): http://www.openwall.com/lists/john-users/2018/07/23/1 … https://github.com/magnumripper/JohnTheRipper/tree/bleeding-jumbo/src/ztex/fpga-sha512crypt …
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High frequency supply decoupling should be handled on chip or in package. Generally too much inductance going through pins to the board, but it will be chip and app dependent.
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Давно и проще - самые прожорливые блоки работают по обоим фронтам, а самые производительные части даже асинхронно (умножение например).
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Any specific examples? I am aware Pentium 4 integer ALUs operated on both edges, but this was since abandoned and it's not a many-core CPU. I am unaware of CPUs with async MUL, are you? AFAIK, most FPGAs don't support flip-flops working on both edges at once (have to choose one).
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