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solardiz's profile
Solar Designer
Solar Designer
Solar Designer
@solardiz

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Solar Designer

@solardiz

@Openwall founder. RTs don't imply agreement with points of view.

openwall.com
Joined August 2012

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    Solar Designer‏ @solardiz Aug 19

    In many-core CPUs does it make sense to run half the cores on inverted clock (or otherwise phase-shifted, for a split into more than two sets) or have that half's flip-flops triggered on negedge to reduce supply voltage ripple? In particular, in FPGA designs? @adolofsson @jangray

    4:14 AM - 19 Aug 2018
    • 9 Retweets
    • 12 Likes
    • bartavelle Royce Williams VfioGaming Rich Felker 𝓐𝓵𝓫𝓮𝓻𝓽 🌵🍺 David Maxwell Nicolás Wolovick Daniel Bilar cryptozeny@JK17+
    2 replies 9 retweets 12 likes
      1. New conversation
      2. Andreas Olofsson‏ @adolofsson Aug 19
        Replying to @solardiz @jangray

        That would depend on the decoupling capacitors and frequency response of your power delivery network, but in general I would say no.

        2 replies 1 retweet 2 likes
      3. Solar Designer‏ @solardiz Aug 19
        Replying to @adolofsson @jangray

        Thanks. Considering DC resistance, it'd reduce the peak voltage drop on PCB traces between the decoupling capacitors and the chip as well as on power distribution on die. I thought this could help. I understand impedance at the original vs. multiplied frequency might matter more.

        1 reply 0 retweets 1 like
      4. Solar Designer‏ @solardiz Aug 19
        Replying to @solardiz @adolofsson @jangray

        We might give this a try in an attempt to get our sha512crypt design to run at the design tools' expected frequency (where it also draws more power, so we suspect supply voltage ripple is the problem): http://www.openwall.com/lists/john-users/2018/07/23/1 … https://github.com/magnumripper/JohnTheRipper/tree/bleeding-jumbo/src/ztex/fpga-sha512crypt …

        1 reply 2 retweets 4 likes
      5. Andreas Olofsson‏ @adolofsson Aug 19
        Replying to @solardiz @jangray

        High frequency supply decoupling should be handled on chip or in package. Generally too much inductance going through pins to the board, but it will be chip and app dependent.

        0 replies 0 retweets 0 likes
      6. End of conversation
      1. New conversation
      2. erthink‏ @LeoYuriev Aug 19
        Replying to @solardiz @adolofsson @jangray

        Давно и проще - самые прожорливые блоки работают по обоим фронтам, а самые производительные части даже асинхронно (умножение например).

        1 reply 0 retweets 0 likes
      3. Solar Designer‏ @solardiz Aug 19
        Replying to @LeoYuriev

        Any specific examples? I am aware Pentium 4 integer ALUs operated on both edges, but this was since abandoned and it's not a many-core CPU. I am unaware of CPUs with async MUL, are you? AFAIK, most FPGAs don't support flip-flops working on both edges at once (have to choose one).

        0 replies 0 retweets 1 like
      4. End of conversation

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