The thread or the gsmarena link ?
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Replying to @bharathguvvala
@slightlylate jumps to misleading conclusions. Just because L2 cache isn't listed, it doesn't mean there is no cache.2 replies 0 retweets 0 likes -
Replying to @TriLinga_ @bharathguvvala
I've been wading through traces and product data sheets for months now. When it's not listed, tends to be tiny (< 2MB total)
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Replying to @slightlylate @bharathguvvala
ARM says Cortex-A53 has a maximum L2 cache of 2 MB. So how can you expect anything more than 2 MB for this design ?
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Replying to @TriLinga_ @bharathguvvala
First, these are reference designs. SoC vendors are free to customise so long as they are ISC compatible.
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This is what Apple started doing as far back as the A7/A8 and has pulled ahead on.
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Next, cache sizings are only one aspect of the total perf question. Instruction dispatch unit count/layout/pipeline matters.
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By simply taking ARM's (slow) design at face value,
@SamsungSemiUS,@MediaTek, and@Qualcomm are failing to compete. It's nuts.2 replies 0 retweets 0 likes -
Replying to @slightlylate @bharathguvvala
Samsung& Qualcomm have their own high-performance CPUs(Mongoose, Kryo). Mediatek is using ARM's Cortex-A73. These are sufficient to compete.
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Nobody's making competitive SoCs in the Android ecosystem. Nobody.
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