This is what Apple started doing as far back as the A7/A8 and has pulled ahead on.
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Next, cache sizings are only one aspect of the total perf question. Instruction dispatch unit count/layout/pipeline matters.
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By simply taking ARM's (slow) design at face value,
@SamsungSemiUS,@MediaTek, and@Qualcomm are failing to compete. It's nuts.2 replies 0 retweets 0 likes -
Replying to @slightlylate @TriLinga_ and
The notion that an SoC vendor is restricted in cache sizing by IP design is nonsensical. The sizes are transparent to software.
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Replying to @slightlylate @TriLinga_ and
That's the thing about the ISC/ISA: it's the only thing you can actually count on as a software engineer. Everything else is an abstraction.
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Replying to @slightlylate @TriLinga_ and
From the perspective of software, a chip with a bigger L1/L2/L3 is _just a faster chip_ (unless you're using vendor extension APIs).
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Replying to @slightlylate @TriLinga_ and
I'm sorry, we're both discussing history and current market structure. "Designed for small die size" has no bearing on either.
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Replying to @slightlylate @TriLinga_ and
SoC vendors have broad leeway here. They can customize cores for whatever workloads they like (hence customizable caches/core-counts!)
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Replying to @slightlylate @TriLinga_ and
From a historical context, the A53 was designed to compete circa '14/'15. It didn't. Poor tradeoffs then.
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Replying to @slightlylate @TriLinga_ and
Those tradeoffs, particularly on 28nm, *continue to be poor* for users on moderately priced devices.
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All of this would be less pressing if we were seeing low-core-count A53s w/ maxed-out caches. Those parts aren't being made/sold.
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Replying to @slightlylate @TriLinga_ and
...and they aren't being made or sold on decent process nodes. It's all crap out here in Android land; the hangover from a bad night out.
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