@slightlylate jumps to misleading conclusions. Just because L2 cache isn't listed, it doesn't mean there is no cache.
I'm sorry, we're both discussing history and current market structure. "Designed for small die size" has no bearing on either.
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SoC vendors have broad leeway here. They can customize cores for whatever workloads they like (hence customizable caches/core-counts!)
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From a historical context, the A53 was designed to compete circa '14/'15. It didn't. Poor tradeoffs then.
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