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From the perspective of software, a chip with a bigger L1/L2/L3 is _just a faster chip_ (unless you're using vendor extension APIs).
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I'm sorry, we're both discussing history and current market structure. "Designed for small die size" has no bearing on either.
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SoC vendors have broad leeway here. They can customize cores for whatever workloads they like (hence customizable caches/core-counts!)
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