The notion that an SoC vendor is restricted in cache sizing by IP design is nonsensical. The sizes are transparent to software.
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That's the thing about the ISC/ISA: it's the only thing you can actually count on as a software engineer. Everything else is an abstraction.
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From the perspective of software, a chip with a bigger L1/L2/L3 is _just a faster chip_ (unless you're using vendor extension APIs).
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