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slightlylate's profile
Alex Russell
Alex Russell
Alex Russell
@slightlylate

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Alex Russell

@slightlylate

Chrome Project 🐡 & Web Standards TL; Blink API OWNER Named PWAs w/ @phae; probably making her ☕ DMs open. Tweets my own; press@google.com for official comms.

San Francisco, The Internet
infrequently.org
Joined December 2010

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    1. Bharath Guvvala‏ @bharathguvvala 16 Oct 2017
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      Bharath Guvvala Retweeted Alex Russell

      Must Read!https://twitter.com/slightlylate/status/919989184881876992 …

      Bharath Guvvala added,

      Alex Russell @slightlylate
      Meet the $100 phone! This is the Moto C Plus: https://m.gsmarena.com/motorola_moto_c_plus-8646.php …
      Show this thread
      1 reply 0 retweets 2 likes
    2. Sasank‏ @TriLinga_ 16 Oct 2017
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      Replying to @bharathguvvala

      The thread or the gsmarena link ?

      1 reply 0 retweets 0 likes
    3. Bharath Guvvala‏ @bharathguvvala 16 Oct 2017
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      Replying to @TriLinga_

      Thread

      1 reply 0 retweets 0 likes
    4. Sasank‏ @TriLinga_ 16 Oct 2017
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      Replying to @bharathguvvala

      @slightlylate jumps to misleading conclusions. Just because L2 cache isn't listed, it doesn't mean there is no cache.

      2 replies 0 retweets 0 likes
    5. Alex Russell‏ @slightlylate 16 Oct 2017
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      Replying to @TriLinga_ @bharathguvvala

      I've been wading through traces and product data sheets for months now. When it's not listed, tends to be tiny (< 2MB total)

      1 reply 0 retweets 0 likes
    6. Sasank‏ @TriLinga_ 16 Oct 2017
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      Replying to @slightlylate @bharathguvvala

      ARM says Cortex-A53 has a maximum L2 cache of 2 MB. So how can you expect anything more than 2 MB for this design ?

      1 reply 0 retweets 0 likes
    7. Alex Russell‏ @slightlylate 16 Oct 2017
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      Replying to @TriLinga_ @bharathguvvala

      First, these are reference designs. SoC vendors are free to customise so long as they are ISC compatible.

      2 replies 0 retweets 0 likes
    8. Alex Russell‏ @slightlylate 16 Oct 2017
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      Replying to @slightlylate @TriLinga_ @bharathguvvala

      This is what Apple started doing as far back as the A7/A8 and has pulled ahead on.

      2 replies 0 retweets 0 likes
    9. Alex Russell‏ @slightlylate 16 Oct 2017
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      Replying to @slightlylate @TriLinga_ @bharathguvvala

      Next, cache sizings are only one aspect of the total perf question. Instruction dispatch unit count/layout/pipeline matters.

      1 reply 0 retweets 0 likes
      Alex Russell‏ @slightlylate 16 Oct 2017
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      Replying to @slightlylate @TriLinga_ @bharathguvvala

      By simply taking ARM's (slow) design at face value, @SamsungSemiUS, @MediaTek, and @Qualcomm are failing to compete. It's nuts.

      10:55 PM - 16 Oct 2017
      2 replies 0 retweets 0 likes
        1. New conversation
        2. Alex Russell‏ @slightlylate 16 Oct 2017
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          Replying to @slightlylate @TriLinga_ and

          The notion that an SoC vendor is restricted in cache sizing by IP design is nonsensical. The sizes are transparent to software.

          1 reply 0 retweets 0 likes
        3. Alex Russell‏ @slightlylate 16 Oct 2017
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          Replying to @slightlylate @TriLinga_ and

          That's the thing about the ISC/ISA: it's the only thing you can actually count on as a software engineer. Everything else is an abstraction.

          1 reply 0 retweets 0 likes
        4. 7 more replies
        1. New conversation
        2. Sasank‏ @TriLinga_ 16 Oct 2017
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          Replying to @slightlylate @bharathguvvala

          Samsung& Qualcomm have their own high-performance CPUs(Mongoose, Kryo). Mediatek is using ARM's Cortex-A73. These are sufficient to compete.

          1 reply 0 retweets 0 likes
        3. Alex Russell‏ @slightlylate 16 Oct 2017
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          Replying to @TriLinga_ @bharathguvvala

          Nobody's making competitive SoCs in the Android ecosystem. Nobody.

          0 replies 0 retweets 0 likes
        4. End of conversation

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