Next, cache sizings are only one aspect of the total perf question. Instruction dispatch unit count/layout/pipeline matters.
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By simply taking ARM's (slow) design at face value,
@SamsungSemiUS,@MediaTek, and@Qualcomm are failing to compete. It's nuts. -
The notion that an SoC vendor is restricted in cache sizing by IP design is nonsensical. The sizes are transparent to software.
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