First, these are reference designs. SoC vendors are free to customise so long as they are ISC compatible.
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This is what Apple started doing as far back as the A7/A8 and has pulled ahead on.
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Next, cache sizings are only one aspect of the total perf question. Instruction dispatch unit count/layout/pipeline matters.
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ARM thinks 2 MB is good enough for this design. So if you think its not enough, show me an A53 implementation with "sufficient" L2 cache.
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