I've been wading through traces and product data sheets for months now. When it's not listed, tends to be tiny (< 2MB total)
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ARM says Cortex-A53 has a maximum L2 cache of 2 MB. So how can you expect anything more than 2 MB for this design ?
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First, these are reference designs. SoC vendors are free to customise so long as they are ISC compatible.
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