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slightlylate's profile
Alex Russell
Alex Russell
Alex Russell
@slightlylate

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Alex Russell

@slightlylate

Chrome Project 🐡 & Web Standards TL; Blink API OWNER Named PWAs w/ @phae; probably making her ☕ DMs open. Tweets my own; press@google.com for official comms.

San Francisco, The Internet
infrequently.org
Joined December 2010

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    Alex Russell‏ @slightlylate 16 Oct 2017
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    Meet the $100 phone! This is the Moto C Plus: https://m.gsmarena.com/motorola_moto_c_plus-8646.php …

    11:11 AM - 16 Oct 2017
    • 18 Retweets
    • 60 Likes
    • Ideas At Random ... adoussot Ismaël Mejía Cory Rylan adam so❤️ Gaurav 👨🏽‍💻🧙🏼‍♂️🐉 Abraham Williams Connor E AJ Klein
    4 replies 18 retweets 60 likes
      1. New conversation
      2. Alex Russell‏ @slightlylate 16 Oct 2017
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        It's currently on offer on Flipkart (homepage, above-the-fold):pic.twitter.com/PBh1zRSgs6

        2 replies 0 retweets 2 likes
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      3. Alex Russell‏ @slightlylate 16 Oct 2017
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        The SoC is quad-core, but let's dig into what that means in practice:https://www.mediatek.com/products/smartphones/mt6737 …

        1 reply 0 retweets 3 likes
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      4. Alex Russell‏ @slightlylate 16 Oct 2017
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        Because this is fab'd on the (zomg bad) 28nm process, thermal concerns keep it clocked to 1.3ghz

        1 reply 0 retweets 2 likes
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      5. Alex Russell‏ @slightlylate 16 Oct 2017
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        Which wouldn't be so bad if it had any cache or if the architecture was modern.

        1 reply 0 retweets 1 like
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      6. Alex Russell‏ @slightlylate 16 Oct 2017
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        No such luck! All 4 cores are last-of-the-in-order-design A53s.

        1 reply 0 retweets 1 like
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      7. Alex Russell‏ @slightlylate 16 Oct 2017
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        And experience tells me that when L2/L3 aren't called out by manufacturer, it's because there isn't any to speak of: https://www.notebookcheck.net/Mediatek-MT6737-SoC-Benchmarks-and-Specs.178416.0.html …

        1 reply 0 retweets 7 likes
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      8. Alex Russell‏ @slightlylate 16 Oct 2017
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        So how should you think about the A53? First, note the phrase "high efficiency" in the marketing material:https://developer.arm.com/products/processors/cortex-a/cortex-a53 …

        1 reply 0 retweets 1 like
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      9. Alex Russell‏ @slightlylate 16 Oct 2017
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        This was not designed to be a speed demon. It was, however, the first core design for Androids that was available in 64-bit...

        1 reply 0 retweets 1 like
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      10. Alex Russell‏ @slightlylate 16 Oct 2017
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        ...this mattered a LOT in 2014 when Android handset makers got their butts handed to them by Apple over 64-bit:https://www.theverge.com/2014/8/27/6076457/htc-desire-510-64-bit-android …

        1 reply 1 retweet 5 likes
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      11. Alex Russell‏ @slightlylate 16 Oct 2017
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        But they did it badly. 28nm was the new hotness -- as it turned out literally. Electron-voltage leakage on the 28nm process was *bad*.

        1 reply 0 retweets 2 likes
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      12. Alex Russell‏ @slightlylate 16 Oct 2017
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        This wasn't entirely unexpected, but the size of the problem on 28nm surprised most everyone. Couldn't frequency scale as a result.

        1 reply 0 retweets 1 like
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      13. Alex Russell‏ @slightlylate 16 Oct 2017
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        ...and *that* mattered because costs for SoCs have a lot to do with die sizes...and the easiest thing to cut is cache.

        1 reply 0 retweets 1 like
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      14. Alex Russell‏ @slightlylate 16 Oct 2017
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        Consumers don't know to look for L2/L3 cache sizes on the tin. How would you even start to explain cache coherence to a punter?

        1 reply 0 retweets 6 likes
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      15. Alex Russell‏ @slightlylate 16 Oct 2017
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        So you don't; you sell core counts.

        1 reply 0 retweets 2 likes
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      16. Alex Russell‏ @slightlylate 16 Oct 2017
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        ...and core counts are a lie. DVFS keeps most cores are spun down most of the time. I go into it a tiny bit here:https://www.youtube.com/watch?v=4bZvq3nodf4 …

        2 replies 1 retweet 7 likes
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      17. Alex Russell‏ @slightlylate 16 Oct 2017
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        But it's really hard to overstate the impact of code and data locality. A bigger cache means you go to main memory less.

        1 reply 0 retweets 2 likes
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      18. Alex Russell‏ @slightlylate 16 Oct 2017
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        Check out the chart here for context: https://www.anandtech.com/show/9837/snapdragon-820-preview/2 …

        1 reply 0 retweets 1 like
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      19. Alex Russell‏ @slightlylate 16 Oct 2017
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        You *badly* want to be in that low/left end of the curve. The easiest way to get that is a bigger cache so more programs do more of the time

        1 reply 0 retweets 1 like
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      20. Alex Russell‏ @slightlylate 16 Oct 2017
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        ...yet, mostly for cost and marketing reasons, nearly all Android-ecosystem SoCs are CPU poor. Many have tiny L2 and little (if any) L3.

        1 reply 1 retweet 2 likes
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      21. Alex Russell‏ @slightlylate 16 Oct 2017
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        MEANWHILE IN CUPERTINO: https://en.wikipedia.org/wiki/Apple_A9  https://en.wikipedia.org/wiki/Apple_A10  https://en.wikipedia.org/wiki/Apple_A11 

        2 replies 1 retweet 4 likes
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      22. Alex Russell‏ @slightlylate 16 Oct 2017
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        Yes, you're reading that right: between the A10 and the A11, Apple went from 3MB L2/4MB L3 to *8MB L2*

        1 reply 2 retweets 6 likes
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      23. Alex Russell‏ @slightlylate 16 Oct 2017
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        For a sense of scale: http://norvig.com/21-days.html#answers … https://people.eecs.berkeley.edu/~rcs/research/interactive_latency.html …

        1 reply 0 retweets 3 likes
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      24. Alex Russell‏ @slightlylate 16 Oct 2017
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        So back to our $100 phone. The slow-clocked (1.3Ghz) A53 cores are missing _any_ discernible cache. What does that mean?

        1 reply 0 retweets 2 likes
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      25. Alex Russell‏ @slightlylate 16 Oct 2017
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        It means that anything that isn't a tight loop on a small amount of data is going to suffer a main-memory read.

        1 reply 0 retweets 1 like
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      26. Alex Russell‏ @slightlylate 16 Oct 2017
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        ...and main-memory reads are 200x more expensive than local (L1) reads. Need that data to keep doing work? Tough luck.

        1 reply 0 retweets 2 likes
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      27. Alex Russell‏ @slightlylate 16 Oct 2017
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        These situations are called "stalls" or "waits"; CPU is spun up, but it's not retiring instructions (doing work): https://en.wikipedia.org/wiki/Wait_state 

        1 reply 0 retweets 2 likes
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      28. Alex Russell‏ @slightlylate 16 Oct 2017
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        ...which means that one of the worst effects of the cores-not-caches tradeoff in this phone is that it loses *power efficiency* too.

        1 reply 0 retweets 5 likes
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      29. Alex Russell‏ @slightlylate 16 Oct 2017
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        The best trade in mobile CPU design today is to swap caches for cores (looking at you @qualcomm, @SamsungSemiUS, & @MediaTek)

        2 replies 0 retweets 7 likes
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      30. Alex Russell‏ @slightlylate 16 Oct 2017
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        So how slow is the @MediaTek MT6737? Lets go to the film! Here are some devices built with this chip:https://www.kimovil.com/en/list-smartphones-by-processor/mediatek-mt6737 …

        2 replies 0 retweets 3 likes
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      31. Alex Russell‏ @slightlylate 16 Oct 2017
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        ...and they all score like this: https://browser.geekbench.com/v4/cpu/4478849 

        2 replies 0 retweets 1 like
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      32. 2 more replies

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