It seems like it may be related to rowhammer. I still find rowhammer stupid, no amount of cache flushing should be able to interfere with proper DRAM refresh yet that's exactly what happens *sigh* That's a bug in the memory controller, not DRAM
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Everyone responsible has done an extraordinary job avoiding responsibility for rowhammer. This should have been a multi-billion-$ (multi-trillion?) recall.
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I think the problem is that it likely affects every x86 CPU in existence. At least Intel ones. Not a feasible recall. Now ok, maybe "stupid" is too harsh (deadlines etc) but still surprised they let that instruction override the refresh mechanism like that.
End of conversation
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Interesting alternative mitigation: 64-bit kernel with support for 64-bit user processes disabled, no way to address kernel mem from userspace.
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It’s my understanding this does not apply to AMD CPU’s.
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Most appropriate use of tl;dr I've seen for a while. Thanks.
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Surely it’s too early for April Fools, right?
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By 'all contemporary CPU' I think you mean all x86 compatible ones - ISTR some features added to ARM years back meant this wouldn't be possible...
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Wow :)
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highly interesting, thanks!
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