Fabian Giesen

@krismicinski, Intel can JIT register allocate stack values?!

something like that, yes. post your code and ask one of the heavy hitters around here like @rygorous or @stephentyrone

You get two loads and one store per cycle these days. (And still have issue slots to spare for other work.) It depends on what you're doing and how you're measuring, but as long as you hit the L1 cache, loads and stores are by no means slow.

Is there extra latency associated with store-to-load forwarding or is that pretty much the same as if a register had been used (assuming the adress computation does not itself stall)?

store to load forwarding is somewhat slower than a regular L1 hit, yes. Assuming you actually get forwarding, ballpark 50% slower. (~6 instead of ~4 cycles latency). If you do things that break forwarding, the penalties can get way bigger, because that requires a partial flush.

But especially x86 has been forced to get really good at loads/stores and store forwarding because 32-bit x86 code is still common and quite register-starved. It takes some effort to make the various tricks not work. :)

Anyway, back to what John said: actually, no memory renaming in any current x86 (that I know of, anyway). Loads/stores do always execute as such. It's just that current machines are really quite good at both. (And have quite the capacity for them!)

wait!!! I thought some smalish number of stack slots really did get effectively registered, is this not that case?