Erika

@rrika9

🏳️‍🌈 abstract things, pretty things, unimportant (gpu) compiler dev (also @rrika@mastodon.social, alt: )

Vrijeme pridruživanja: listopad 2015.

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  1. Prikvačeni tweet
    2. ožu 2019.
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  2. prije 5 sati

    not sure if that'd interact nicely with nested loops though

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  3. prije 5 sati

    block 0: %i = phi 0, %next_i %is = phi {}, %next_is %next_i = 1 + %i %next_is = %is ∪ {%i} branch block 0 if %i < 10 else block 1 block 1: %todo = phi %is, %ntodo branch exit if %todo empty else block 2 block 2: ... (%i, %ntodo) = pop_any %todo branch block 1

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  4. prije 5 sati

    maybe with a native set type? before: block 1: %i = phi 0, %next_i branch block 2 if %i < 10 else exit block 2: ... %next_i = 1 + %i branch block 1 exit

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  5. prije 5 sati

    How would one encode in a compiler IR that the iteration order of a loop is irrelevant. If it the control flow was structured, it'd be as easy as a flag on the loop, but for arbitrary cfgs, how does one ensure transformations don't break the annotation?

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    2. velj
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  7. proslijedio/la je Tweet
    prije 13 sati

    Still really proud of this lineup render, and none of them higher than 300 polys each! What arctic vehicle should I do next? I’ve always thought that Snowmobiles were super cool, and a retro one might be rad.

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  8. proslijedio/la je Tweet
    prije 19 sati

    it warms my heart to see people reuse Glasgow applets (like the JTAG code) completely outside of Glasgow; I never specifically intended for this, but I tried to make them simple and generic, and turns out you can just graft many of them to any random UART you have around

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  9. proslijedio/la je Tweet
    2. velj

    Q: when should I use \nopagebreak in TeX? A:

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  10. proslijedio/la je Tweet
    2. velj

    Most notable moment of FOSDEM for me will be my girlfriends walking into the BSD devroom and the KDE speaker pointing to our row and saying "the sharks are over there"

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  11. proslijedio/la je Tweet
    2. velj

    My crazy, half-finished attempt to embed a Controlled Natural Language into Lean 4 I demoed today

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  14. proslijedio/la je Tweet
    24. sij

    After smashing a few bugs, the network generates output again. Keras says the accuracy is over 97%, and there is a very noticeable improvement. Here's the section I showed earlier, before and after these changes.

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    1. velj
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  16. proslijedio/la je Tweet
    10. sij

    And the fun begins. Using my tried and proven technique of instantiating UARTs on all IOs. Each UART sends it's number out it got in the generate block. Just probing now on the pins and the oscope serial decoder spits out the corresponding pin number 😎

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  18. 1. velj

    fun thing I realized on the project: there was no need to hook up a logic analyzer since the FTDI that usually does the programming can be repurposed as one by sigrok and is conveniently -already connected- to the wires I'm interested in

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  19. 1. velj

    \o I'm back from my Twitter break and I have one project update! I connected my FPGA to its own JTAG and had it update its configuration on the fly. 🌈 I hope to polish and publish some code in the next months whenever I can squeeze it between fulltime job and the rest of my life

    photo of an ECP5 development board with a bundle of rainbow colored cables going from the I/O pins to the JTAG pins
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  20. proslijedio/la je Tweet
    16. sij
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  21. 17. sij

    when you hear someone use 'student' as a synonym for 'unpaid/underpaid worker' T______T

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