it might have been obvious to you that the problem you initially stated (partitioning for min register usage) was in fact a scheduling problem but it sure wasn't for me until I worked that through!
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Replying to @FioraAeterna @stephentyrone
well, here you go. http://lmgtfy.com/?q=scheduling+expression+dags+for+minimal+register+need …
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Replying to @FioraAeterna @stephentyrone
no seriously the first hit is a paper with an algorithm
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Replying to @FioraAeterna @stephentyrone
the minimum schedule induces extra edges in the graph (corresponding to ordering in the schedule) that connect what would otherwise be parallel components of your graph.
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I believe if your program is in SSA, then you can just assign registers first come first serve and it ends up optimal. Could be wrong.
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Replying to @pcwalton @FioraAeterna and
See https://github.com/Cretonne/cretonne/blob/master/docs/regalloc.rst … for details—this is how Cretonne does it.
10:51 AM - 12 Mar 2018
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