Reading a bit about Go's goroutine scheduler. Sounds like it tries to solve many of the same problems a GPU's shader core does. # threads ("goroutines") >> # of simds ("OS threads"), fast switching, small stacks, minimal fairness, turn blocking calls into async calls.
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I assume you’re referring to Cell’s SPUs. From what I understand, they are SIMD cores with local SRAMs, no access to shared memory, that communicate via message passing and explicit DMAs. That not really what I’m envisioning.. :)
Thanks. Twitter will use this to make your timeline better. UndoUndo
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More like barrel processors, I assume? (Tera MTA, that one funny PIC implementation, Cray's first version of the graph processing machine for the TLAs)
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I haven’t heard of any of these! I’ll have to check these out :)
End of conversation
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