It would be nice if we could have a RISC-V do-over that’s just an average, boring ISA, nothing weird or experimental.
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It's not "de factor required" and SiFive's E20 is just a config for their core generator. I'm sure they'll happily generate an embedded core without M if a customer asks for that. (And I know that there are deep embedded risc-v cores without M in use in ASICs already.)
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Yeah, sounds reasonable.
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Likewise, DIV.
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