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pcwalton's profile
Patrick Walton
Patrick Walton
Patrick Walton
@pcwalton

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Patrick Walton

@pcwalton

Research engineer at Mozilla

San Francisco, CA
pcwalton.github.io
Joined November 2009

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    1. Claire Xen  🏳️‍🌈 🏳️‍⚧️ 🧙🏻‍♀️‏ @oe1cxw 11 Oct 2019
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      What I find most funny about ARM moving to allow custom ISA extensions is that in last year's "risc-v basics" smear campaign one of their main arguments against RISC-V was that it'd be unfathomably bad that RISC-V allows custom ISA extensions bc that would lead to fragmentation.

      5 replies 18 retweets 95 likes
    2. Rich Felker‏ @RichFelker 11 Oct 2019
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      Replying to @oe1cxw

      FWIW, I think the argument was correct. I wish RISC-V and others would explore ways to do custom extensions that don't clash with ISA encoding space.

      3 replies 0 retweets 4 likes
    3. Patrick Walton‏ @pcwalton 11 Oct 2019
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      Replying to @RichFelker @oe1cxw

      It would be nice if we could have a RISC-V do-over that’s just an average, boring ISA, nothing weird or experimental.

      1 reply 0 retweets 3 likes
    4. Rich Felker‏ @RichFelker 11 Oct 2019
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      Replying to @pcwalton @oe1cxw

      I don't see much of it as weird or experimental, just reasonable risc without all the mips badness copied like everyone else did.

      3 replies 0 retweets 3 likes
    5. Patrick Walton‏ @pcwalton 11 Oct 2019
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      Replying to @RichFelker @oe1cxw

      What are your thoughts on https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d9982f7618ef68 … ?

      3 replies 0 retweets 5 likes
    6. Rich Felker‏ @RichFelker 11 Oct 2019
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      Replying to @pcwalton @oe1cxw

      Roughly half is moderately serious, half is pointless pedantry about things that don't matter or complaints about good choices.

      1 reply 0 retweets 2 likes
    7. Rich Felker‏ @RichFelker 11 Oct 2019
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      Replying to @RichFelker @pcwalton @oe1cxw

      Atomics being optional is absolutely wrong. Non-SMP core can implement lr/sc trivially and should be required to. Likewise for mul but not quite as serious since it *can* be emulated in sw.

      3 replies 0 retweets 1 like
    8. Steve Canon‏ @stephentyrone 11 Oct 2019
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      Replying to @RichFelker @pcwalton @oe1cxw

      The MUL thing is silly because even if the HW ends up doing the same thing as SW in some cases, it’s always at least as efficient, and usually much more. And it’s such a common operation that not having it in base badly fractures binaries—you *have* to use it when available.

      1 reply 0 retweets 3 likes
    9. Steve Canon‏ @stephentyrone 11 Oct 2019
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      Replying to @stephentyrone @RichFelker and

      If you aren’t going to put MUL and barebones atomics in the base ISA, you barely have an ISA; you need to have at least two versions of everything anyway.

      2 replies 0 retweets 2 likes
    10. Steve Canon‏ @stephentyrone 11 Oct 2019
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      Replying to @stephentyrone @RichFelker and

      I mean, FFS, even a Cortex-M0 has MUL for exactly this reason. It can optionally be 32 cycles, but it’s always present.

      1 reply 0 retweets 3 likes
      Patrick Walton‏ @pcwalton 11 Oct 2019
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      Replying to @stephentyrone @RichFelker @oe1cxw

      Can they just issue a revision to make mul non-optional from 2020 onward or whatever?

      4:55 PM - 11 Oct 2019
      • 1 Like
      • Rich Felker
      2 replies 0 retweets 1 like
        1. New conversation
        2. Kevin‏ @ElectronicKiwi 11 Oct 2019
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          Replying to @pcwalton @stephentyrone and

          So far, every non-hobbyist core that I have seen implements multiplication in hardware. E.g., SiFive's smallest core the E20 implements RV32IMC:https://www.sifive.com/cores/e20 

          1 reply 0 retweets 0 likes
        3. Patrick Walton‏ @pcwalton 11 Oct 2019
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          Replying to @ElectronicKiwi @stephentyrone and

          If mul is already de facto required they should just make it officially required, IMO.

          3 replies 0 retweets 2 likes
        4. 1 more reply
        1. Rich Felker‏ @RichFelker 11 Oct 2019
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          Replying to @pcwalton @stephentyrone @oe1cxw

          Making lr/sc non-optional is a much more critical fix needed.

          0 replies 0 retweets 1 like
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