What I find most funny about ARM moving to allow custom ISA extensions is that in last year's "risc-v basics" smear campaign one of their main arguments against RISC-V was that it'd be unfathomably bad that RISC-V allows custom ISA extensions bc that would lead to fragmentation.
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Replying to @oe1cxw
FWIW, I think the argument was correct. I wish RISC-V and others would explore ways to do custom extensions that don't clash with ISA encoding space.
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Replying to @RichFelker @oe1cxw
It would be nice if we could have a RISC-V do-over that’s just an average, boring ISA, nothing weird or experimental.
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I don't see much of it as weird or experimental, just reasonable risc without all the mips badness copied like everyone else did.
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Replying to @RichFelker @oe1cxw
What are your thoughts on https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d9982f7618ef68 … ?
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As a general statement, the common theme of most of these complaints is the minimalist core they standardized and froze for all time does not contain many desirable instructions. But many of these complaints have been resolved by instructions added in draft versions of the ISA
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In that regard, I'd say it can be likened to the "batteries included std" debate. To get to the point of a permanently frozen core ISA, they pursued a minimum viable product, perhaps to a fault, but that isn't intended to be the steady state.
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That’s good to hear.
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