x86 is space efficient, you say? AArch64: sub x9,x10,x11: 4 bytes. x86-64: mov r9,r10; sub r9,r11: 6 bytes. (Can’t use LEA here.) AArch64: sub x9,x10,#1234: 4 bytes. x86-64: lea r9,[r10-1234]: 7 bytes.
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This talk from FOSDEM looks at binary sizes for RISCV :https://fosdem.org/2019/schedule/event/riscvcompact/ …
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Yeah. To make the comparison meaningful though I need a way to exclude differences due to float ABI. Softfloat quad kills size on archs that have ld=quad.
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I think just measuring .o files (to omit libgcc softfloat in .so) and excluding *l math funcs would be mostly fair.
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In my own tests (code-density), Thumb2 and x86 (32-bit) did pretty well, followed by RVC, with Thumb & SH4 shortly after. The fixed-length 32b ISAs followed after this. Though, "useful work per instruction" is weaker with fixed-length 16b ISAs (ex: Thumb & SH4) vs 32b ISAs, ...
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Work per instruction: a 16b ISA may need ~ 30-40% more ops for a similar amount of work vs 32b, but the ops are half the size, so final binary is ~60-70% the size. Variable-length (16/32) ISAs (ex: Thumb2 and RVC) fare better on both code-density and perf, but are more complex.
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