Wow, this is such a cool idea. Translating regular instructions to SIMD instructions in order to run 16 copies of the same program at once, for fuzzing!https://gamozolabs.github.io/fuzzing/2018/10/14/vectorized_emulation.html …
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Replying to @comex @RichFelker
Yeah, AVX-512 is really powerful. I wonder if the endgame of AVX-512 is using it for their GPU ISA, Larrabee-style.
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I’m not sure that they’ll literally share the same *cores* anytime soon. But sharing the same ISA (at least in part) seems reasonable to me. What I was imagining was CPU-like “big” x86 cores and GPU-like “little” x86 cores on the same die sharing a single SIMD ISA.
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Isn’t that pretty much exactly Larrabee though? Larrabee was a separate chip rather than on-die, and its 512-bit instructions were slightly different from AVX-512, but other than that it’s the same idea. I guess a new attempt could be less minimalist wrt graphics-specific HW.
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Well, I don’t see the point of having two vector ISAs (Gen) and SIMD (AVX-512) that largely overlap in functionality but are just incompatible, are programmer-exposed, and ship on the same die.
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See https://software.intel.com/en-us/articles/introduction-to-gen-assembly … — it’s basically like AVX-512 but just incompatible.
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Like, I’m sure Intel would prefer to only have one compiler backend to maintain…
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Any compiler backend maintained by Intel is going to be a joke, just a spec benchmark ad for their chips.
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Oh, also I just remember than Intel already did one ISA consolidation: Intel ME used to be ARC and is now x86.
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Glad the ISA for my box's backdoors has been consolidated...
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