Wow, this is such a cool idea. Translating regular instructions to SIMD instructions in order to run 16 copies of the same program at once, for fuzzing!https://gamozolabs.github.io/fuzzing/2018/10/14/vectorized_emulation.html …
-
-
Overlapping and incompatible SIMD on the same die is pretty much what we do with CPUs and GPUs on other chips…
-
I mean, sure, but is there any good reason for it other than history?
-
I admit I’m biased here, given that I may be writing a CPU SIMD version of WebRender and so the idea of sharing code between CPU and GPU is very relevant to me ;)
-
Maybe for CPUish SIMD it’s helpful to have lots of complications and for GPUish SIMD it’s not worth the silicon?
-
Decode die area is probably the main reason I can think of to not do it, yeah. (For x86 anyway.)
-
GPUs want fancy thread logic and massive register sets. That might conflict with 512-bit wide registers. Dunno.
-
The super wide registers are actually the least interesting part of AVX-512 :)
-
And the most problematic.
End of conversation
New conversation -
-
-
See https://software.intel.com/en-us/articles/introduction-to-gen-assembly … — it’s basically like AVX-512 but just incompatible.
-
Like, I’m sure Intel would prefer to only have one compiler backend to maintain…
-
Any compiler backend maintained by Intel is going to be a joke, just a spec benchmark ad for their chips.
-
Oh, also I just remember than Intel already did one ISA consolidation: Intel ME used to be ARC and is now x86.
-
Glad the ISA for my box's backdoors has been consolidated...
End of conversation
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.