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pcwalton's profile
Patrick Walton
Patrick Walton
Patrick Walton
@pcwalton

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Patrick Walton

@pcwalton

Research engineer at Mozilla

San Francisco, CA
pcwalton.github.io
Joined November 2009

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    1. Patrick Walton‏ @pcwalton 29 Jul 2018
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      Specifically, a call to objc_msgSend would have this fast path: cbz self,cache_miss ; nil check ldp type/targetcache ; compiler generates a slot ldr self->isa cmp typecache,isa bne cache_miss br targetcache

      2 replies 0 retweets 2 likes
      Show this thread
    2. Joe Groff‏ @jckarter 29 Jul 2018
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      Replying to @pcwalton

      I bet @gparker must've tried something along those lines in the past...

      1 reply 0 retweets 1 like
    3. Greg Parker‏ @gparker 4 Aug 2018
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      Replying to @jckarter @pcwalton

      Two problems: One, many call sites really want a two-entry cache (mutable and non-mutable class, for example). Two, it costs too much dirty memory to do this everywhere so you need some way to choose at compile time where to apply it.

      2 replies 0 retweets 3 likes
    4. Patrick Walton‏ @pcwalton 4 Aug 2018
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      Replying to @gparker @jckarter

      Yeah, you can chain them to make polymorphic ICs (all JS engines do this). Can you use PGO to determine which call sites are hot?

      1 reply 0 retweets 1 like
    5. Patrick Walton‏ @pcwalton 4 Aug 2018
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      Replying to @pcwalton @gparker @jckarter

      It’s hard to believe that devirtualization is never worth it. objc_msgSend is pretty much always a BTB miss and that’s gotta hurt…

      2 replies 0 retweets 1 like
    6. Joe Groff‏ @jckarter 4 Aug 2018
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      Replying to @pcwalton @gparker

      That’s not really true on newer architectures. Branch prediction with history in practice predicts msgSend fairly well

      2 replies 0 retweets 2 likes
    7. Patrick Walton‏ @pcwalton 4 Aug 2018
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      Replying to @jckarter @gparker

      Also I didn't see anything about BTB history in https://xania.org/201602/bpu-part-three … and follow-up posts: it seems like just a plain old address cache...

      1 reply 0 retweets 0 likes
    8. Greg Parker‏ @gparker 5 Aug 2018
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      Replying to @pcwalton @jckarter

      I don’t know much about the Intel side or the specific algorithms on any architecture. If I remember correctly Apple’s ARM CPU designers were once worried about the high mispredict rates they observed in objc_msgSend, but then they solved it with no software changes.

      1 reply 0 retweets 2 likes
    9. John McCall‏ @pathofshrines 5 Aug 2018
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      Replying to @gparker @pcwalton @jckarter

      My understanding is that history was always good enough, and the misprediction problem was just that objc_msgSend introduced so many indirect branches that it was blowing out their cache.

      1 reply 0 retweets 0 likes
    10. Patrick Walton‏ @pcwalton 5 Aug 2018
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      Replying to @pathofshrines @gparker @jckarter

      Thinking about it, I guess what Apple’s ARM CPU is probably doing is keying the BTB off not just PC like Intel does, but the (LR, PC) pair. That would give the behavior you describe, because LR is different for each objc_msgSend call.

      1 reply 0 retweets 1 like
      Patrick Walton‏ @pcwalton 5 Aug 2018
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      Replying to @pcwalton @pathofshrines and

      This is especially easy to do on ARM because you have a link register. Anyway, I think you could get the same effect on x86 w/o increasing mem usage by mmap-ing in objc_msgSend at different addresses and having the compiler emit calls to a random one at each site…VIPT abuse ;)

      2:49 PM - 5 Aug 2018 from Dogpatch, San Francisco
      2 replies 0 retweets 0 likes
        1. New conversation
        2. Joe Groff‏ @jckarter 5 Aug 2018
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          Replying to @pcwalton @pathofshrines @gparker

          The lower tech trick is to split up lookup and dispatch, so the branch itself always has a unique address. Even that had marginal or inconsistent benefit on x86 in tests from what I hear

          1 reply 0 retweets 0 likes
        3. Patrick Walton‏ @pcwalton 5 Aug 2018
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          Replying to @jckarter @pathofshrines @gparker

          Huh, surprising that that isn’t a significant improvement. It hits the C++-like paths that Intel optimizes for…

          0 replies 0 retweets 0 likes
        4. End of conversation
        1. New conversation
        2. John McCall‏ @pathofshrines 5 Aug 2018
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          Replying to @pcwalton @gparker @jckarter

          Matt Godbolt’s tests showed that Haswell and Ivy Bridge have a 4096-entry 4-way BTB, so there’s your hard cap on how many indirect branches you can do before you start getting punished.

          1 reply 0 retweets 1 like
        3. John McCall‏ @pathofshrines 5 Aug 2018
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          Replying to @pathofshrines @pcwalton and

          And note that there are other indirect branches in play, such as when calling objc_msgSend itself.

          0 replies 0 retweets 0 likes
        4. End of conversation

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