Static
I disassembled all libraries and binaries in all riscv64 debian packages and counted how often each individual instruction is used: http://svn.clifford.at/handicraft/2018/rvinsfreq/combined.txt … (The most frequently used instruction is "http://c.mv ", followed by "auipc", "addi", and "jal".)
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Did you also check for instruction sequences? We did this for OpenRISC many years ago to get input about useful instructions to add to a future or2k ISA. Never got to do a or2k though as
@risc_v came and implemented basically everything we had planned to do (and likely better) -
I did look at sequences in this experiment from last year: http://svn.clifford.at/handicraft/2017/bitcode/ …
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macro-op fusion pattern matching would be useful. i.e. pairs where the temporary in the first instruction overwrites the second. However there is a chicken and egg problem because to properly exploit macro-op fusion, the compiler needs rules to emit the pairs.
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What’s worse is that the instruction scheduling you should do for simple macro-op fusion is the exact *opposite* of what you should do for a simple in-order superscalar processor. I.e. deliberately put dependent instructions together instead of deliberately separating them.
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GCC also uses different strategies for different ISAs. Because RISC-V lacks scaled indexes loads, GCC appears to emit multiple copies of the loop induction variable for access to arrays of different strides. GCC would need rules to take advantage of macro-op fusion.
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The x86 register-memory for example creates LOAD-OP ; ALU-OP pairs where the implicit temporary would be overwritten if there were macro-op fusion rules (AGU ALU bypassing into the Load Store Unit). Dependent or temporal parallelism vs Independent or spatial parallelism.
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