This commit in the RISC-V spec https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982 … and this commit in spike https://github.com/riscv/riscv-isa-sim/commit/d336aee08ba9c5715d5d7836a39003e62ee4ada8 … changed C.LWSP with rd=0 from being reserved to being a legal instruction.
-
Show this thread
-
-
Replying to @PLT_cheater
Because it means that valid code that compilers might generate for v2.3 and latter of the spec will trigger an illegal instruction trap on the processors that implemented the old version of the spec correctly.
1 reply 1 retweet 2 likes -
Replying to @oe1cxw @PLT_cheater
The other direction (changing it from legal to reserved) would be less problematic, since that would just mean that older cores implement an instruction that newer compilers will never generate.
1 reply 1 retweet 1 like -
Replying to @oe1cxw @PLT_cheater
Also: People are telling me we have not enough reserved compressed encoding space for XBitmanip c.not, c.neg, c.brev instructions (which would take up 24 reserved code points in the encoding space). This change just threw away 64 reserved code points for nothing.
2 replies 1 retweet 4 likes -
Replying to @oe1cxw @PLT_cheater
Tell me if I'm missing something, but wouldn't using the 24 reserved code points for XBitmanip also be a backwards-incompatible change?
1 reply 0 retweets 0 likes
No, because Xbitmanip is an ISA extension RV32IC and RV32IC_Xbitmanip are two different ISA. This is not proposing to change the frozen RV32IC ISA.
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.