Calling all experts: is there a way to beat the default ripple-carry adder for an unpipelined 64-bit FPGA adder (especially on Altera)? My creative attempt couldn't. @oe1cxw @jangray @elaforest @zipcpu @whitequark
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Check wikipedia's article for both carry save and carry lookahead adders. I'm not sure of the impact they will have on an
#FPGA, but they are at least partial solutions to this problem.
Carry save adders can help a lot if you have long chains of additions. I don't know anything about Altera carry primitives, but in general it is difficult to beat the hard silicon carry chain using look-ahead adders in FPGA logic. You'd need to add really large numbers..
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Now I haven't tried it on FPGAs, but I know that for ASIC flows, there's quite a difference between using ripple-carry adders and carry-save adders in multipliers. For just an adder, I would expect carry-look-ahead adders would beat the carry chain for very large* operand sizes.
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The Behrooz Parhami book on Computer Arithmetic has a chapter on FPGA optimized arithmetic units. If memory serves if it's 8-12 bit adder then RCA is good; Carry Skip or Carry Select adders are well suited over the 8-12bit range. Carry Save is good for multi-operand adders.
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These are the relevant references from the Parhami book: 1) C. Select: http://ww1.microchip.com/downloads/en/AppNotes/DOC0467.PDF … 2) C. Skip: https://cc-webshop.com/Circuit-Cellar-Issue-148-November-2002-PDF-FI-2002-148.htm?categoryId=-1 … 3) Carry Chains on FPGA: https://ieeexplore.ieee.org/document/831434/ … The circuit cellar issue can be found on Internet Archive but not sure about copyright.
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Agree. Certain Alters devices start using lut_type cin type from adders with more than 6 bit input, forcing the carry chain between luts. If you are using quartus or another tool you must me able to disable it. See the advanced synthesis cookbook.
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