This commit in the RISC-V spec https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982 … and this commit in spike https://github.com/riscv/riscv-isa-sim/commit/d336aee08ba9c5715d5d7836a39003e62ee4ada8 … changed C.LWSP with rd=0 from being reserved to being a legal instruction.
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It says “not expected to change” before ratification not “will not change”.
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Yes. But that's what was said a lot. (Keynotes at risc-v workshops and such.) There was a big fuzz about 2.x being frozen.
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There are a very small number of RISC-V cores in the wild. They are either FPGA (malleable), deeply embedded (code will never change), or SiFive. The impact of even an incompatible change right now would be small. Not so in a year or two.
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The whole reason for freezing the ISA is to encourage more implementations. Making changes to the frozen ISA is counterproductive. Especially if it is such a pretty thing.
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