This commit in the RISC-V spec https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982 … and this commit in spike https://github.com/riscv/riscv-isa-sim/commit/d336aee08ba9c5715d5d7836a39003e62ee4ada8 … changed C.LWSP with rd=0 from being reserved to being a legal instruction.
A jump from v2 to v3 may do that. That's because RV32I2 and RV32I3 are different ISAs, thus have different ISA subset names. But 2.2 and 2.3 are both RV32I2 and they may only differ in resolving ambiguities and holes. That is the promise given by the foundation to implementers.
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Maybe, though I haven’t seen that written anywhere.
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