This commit in the RISC-V spec https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982 … and this commit in spike https://github.com/riscv/riscv-isa-sim/commit/d336aee08ba9c5715d5d7836a39003e62ee4ada8 … changed C.LWSP with rd=0 from being reserved to being a legal instruction.
What you mean is for new extensions. E.g. RV32I code should run on an RV32IM machine. But within an extension backward compatibility goes both ways. If I make a RV32I core now it should be able to execute RV32I code generated by a compiler 10 years from now.
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I don’t think that’s true. v3 RV32I can include opcodes not present in v2 RV32I. You’ll need to tell your future compiler to restrict itself to v2 opcodes.
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A jump from v2 to v3 may do that. That's because RV32I2 and RV32I3 are different ISAs, thus have different ISA subset names. But 2.2 and 2.3 are both RV32I2 and they may only differ in resolving ambiguities and holes. That is the promise given by the foundation to implementers.
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Also, your old core can execute new instructions via trap and emulate. Hopefully not too frequently!
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