This commit in the RISC-V spec https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982 … and this commit in spike https://github.com/riscv/riscv-isa-sim/commit/d336aee08ba9c5715d5d7836a39003e62ee4ada8 … changed C.LWSP with rd=0 from being reserved to being a legal instruction.
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I used to have a formally verified correct RISC-V core. With the release of v2.3 it will be out of spec. What happened to no backwards incompatible changes after v2.0? What happened to spike is the executable golden reference? It's all lies..
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Rocket of course used to be out of spec up to and including v2.2 of the spec. Starting with v2.3 rocket will magically be in spec and every other implementation that did it correct before will suddenly be in violation of the spec. Nothing matters.
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Replying to @oe1cxw
So they changed the spec to match the Rocket implementation!?!
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And doing it the other way around would have preserved more of the (precious) reserved C opcode space and all cores (including rocket) would be backwards compatible, because accepting illegal insn as legal is always okay. (Because it might as well be a custom vendor extension.)
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